Shared Caching


Chip multiprocessors often provide at least one level of on-chip cache that is shared among the multiple cores. This project is exploring new thread schedulers and architectural enhancements in order to reduce the number of shared cache misses for multi-threaded programs. The thread scheduler takes advantage of the potential overlap in memory references among threads working on the same program, to keep working set sizes small. This dramatically decreases the working set size compared with previous scheduling approaches, potentially reducing the number of misses by orders of magnitude. Key goals of our approach include (1) existing programs need not be modified in order to get good many-core cache performance, and (2) the scheduler provides provably good cache performance for any program with good single-core cache performance.


Publications


Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasilis Liaskovitis, Anastasia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, N. Hardavellas, Todd C. Mowry and Chris Wilkerson. Scheduling Threads for Constructive Cache Sharing on CMPs. In Proceedings of the 19th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA'07), San Diego, CA, June 2007.

Vasilis Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastasia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Michael Kozuch, Todd C. Mowry and Chris Wilkerson. Parallel Depth First vs. Work Stealing Schedulers on CMP Architectures. Brief Announcement in Proceedings of the 18th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA'06), Cambridge, MA, July-August 2006.

Guy E. Blelloch and Phillip B. Gibbons. Sharing a Cache Among Threads. In Proceedings of the 16th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA'04), Barcelona, Spain, June 2004.

Researchers